The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More particularly, the present invention relates to a semiconductor device having an external electrode terminal formed using the Damascene technique and a method for manufacturing such a semiconductor device.
Due to the increased integration, density, and speed of semiconductor devices, wiring that enables higher performance is desired. In the prior art, the material used for wiring is mainly aluminum. However, there is a tendency of electromigration occurring when using aluminum wires. Accordingly, copper has gathered attention as a material that has lower resistance than aluminum and resists electromigration. Copper wires contribute to increasing the speed of semiconductor devices and prolonging the life of semiconductor devices.
In the prior art, copper wires are manufactured using the Damascene technique. A groove is first formed in a dielectric film having a flat surface. The groove is then filled with a metal material. The metal material is then flattened so that the upper surface of the metal material becomes flush with the surface of the dielectric film. This manufactures metal wires. Accordingly, the Damascene technique is a relatively simple method for manufacturing metal wires and easily manufactures copper wires, which cannot be formed through dry etching.
In the prior art, a chemical mechanical polish (CMP) technique is used to flatten the metal material. The CMP technique is a process that combines etching and mechanical polishing and is optimal for flattening relatively large areas. A flattened semiconductor device is manufactured using the Damascene technique to form wires and using the CMP technique to flatten each layer of the semiconductor device.
As shown in FIG. 1, in an integrated circuit of a semiconductor device, an external electrode terminal, such as pad P, is larger than other wires. It is thus difficult to form a flat pad P when using the CMP technique and the Damascene technique.
The pad P is an electrode for connecting a substrate, on which an integrated circuit is formed, to an external circuit. The pad P is connected to the external circuit by a wire w and a lead frame L. As shown in FIG. 2, the pad P includes a lower pad P1, an intermediate pad P2, and an upper pad P3. The size B of each of the pads P1, P2, P3 is larger than the size A of an element in the integrated circuit. In the actual semiconductor device, the size B of the pads P1, P2, P3 is several hundred times larger than the size A of the element.
The lower pad P1 and the intermediate pad P2 are not directly connected to the wire w but have the same size as the upper pad P3. This is to connect the upper pad P3 to the intermediate and lower pads P1, P2 in an aligned state and to test the contact between the semiconductor device and the external device with the lower and intermediate pads P1, P2 before forming an upper wiring layer.
A method for forming the relatively large pads P1, P2 using the Damascene technique at the same time as when forming an element region will now be discussed.
A groove formed in a dielectric film is first filled with a metal material of the pads P1, P2, P3. The upper surfaces of the pads P1, P2, P3 are then flattened using the CMP technique. However, the upper surface of the metal filled in the groove, which has a relatively large opened area, becomes lower than the surface of the dielectric film. This is a problem unique to the CMP technique and is referred to as dishing. Dishing decreases the flatness of the semiconductor device. Further, when the upper layer undergoes a lithography process, dishing may hinder focusing.
A prior art pad forming process and its shortcoming will now be discussed in more detail with reference to FIGS. 3a to 3g. 
Referring to FIG. 3a, in the prior art, a dielectric film 110 is first deposited on a substrate 101. A relatively large pad formation region 110h is formed in the dielectric film 110. Copper 111′ is applied to the dielectric film 110 and the substrate 101 and filled in the pad formation region 110h. 
Then, the upper surface of the copper 111′ is flattened using the CMP technique to form a pad 111 with the dielectric film 110 functioning as a stopper film. In this state, as shown in FIG. 3b, dishing occurs in the copper 111′ in the pad formation region 110h, or the pad 111. Thus, the upper surface of the pad 111 is not flush with the upper surface of the dielectric film 110.
Further, when forming another layer on the pad 111 and the dielectric film 110 to manufacture a semiconductor device having a multilayer structure, dishing decreases the flatness of each layer.
A process for manufacturing a semiconductor device having a multilayer structure will now be discussed with reference to FIGS. 3c to 3e. An interlayer dielectric film 120 is formed on the pad 111 and the dielectric film 110 (FIG. 3c). Contact holes 121 are then formed in the interlayer dielectric film 120 (FIG. 3d). A metal layer 122′ is then applied to the interlayer dielectric film 120 so that the contact holes 121 are filled with metal, which is used to form plugs 122 (FIG. 3e). The metal layer 122′ is etched to form the plugs (FIG. 3f). As shown in FIG. 3g, a pad 131, which is connected to the plugs 122, is formed. The lower layer pad 111 is connected to the upper layer pad 131 by the plugs 122.
Dishing also occurs when forming elements other than the pads 111, 131 using the Damascene technique. Thus, the flattening of a flat semiconductor device is difficult.